1. Field of the Invention
This invention relates to the manufacture and testing of field effect transistors and more particularly to techniques for characterizing instability mechanisms found in certain types of field effect transistors by accelerating the effects of these mechanisms.
2. Description of the Prior Art
Although the metal-insulator-semiconductor field-effect transistor (MISFET) is conceptually the oldest type of active semiconductor device, early attempts to fabricate devices were frustrated because of the presence of high surface state densities at the interface between the semiconductor and the gate insulation. The use of a silicon substrate with thermally produced silicon dioxide as the gate insulator enabled the first successful MISFET to be made as early as 1960. Yet the successful manufacture of MISFETs is still today plagued with instability problems resulting from various charge effects in the insulating or passivating layers essential for field effect operation. Various polarization effects found to alter MISFET operating characteristics are reviewed by Grove and Deal in the Transactions of the Metallurgical Society of AIME, Volume 242, March 1968, pages 512-523.
Various specific mechanisms have been previously observed which enable charged carriers to be injected into MIS insulating layers. Nicollian et al. reported in Applied Physics Letters, Vol. 15, No. 6, Sept. 15, 1969, pages 174-177, that high AC fields applied to MOS capacitors could cause avalanche injection of hot minority carriers into silicon dioxide from a silicon substrate. In order to establish a high enough field within the substrate to cause impact ionization, or avalanching, it was necessary to use a sinusoidal electric field to prevent the formation of an inversion layer which would tend to reduce the effective field required for avalanching. Such unusual stress conditions are not found in the normal operation of MISFETs and direct surface avalanching is not a recognized instability problem in devices used in actual circuits today. Another instability phenomenon is that of majority carrier injection caused by avalanching the drain to substrate junction of an MOSFET. Hara et al reported in the Japanese Journal of Applied Physics, Vol. 9, No. 9, September 1970, pages 1103-1112, that if the reverse bias voltage on the drain is increased beyond a critical breakdown value, in the presence of a low gate voltage, avalanching occured causing injection of majority carriers, holes for p-type substrates, from the silicon substrate to the gate dielectric. Since voltages as high as the required p-n junction avalanche breakdown voltage are rarely seen in actual circuits, drain avalanche caused injection is not a significant instability problem. Erb et al described a "stacked gate tetrode" in the IEEE Transactions on Electron Devices, Vol. ED-18, No. 2, February 1971, pages 105-109. This multiple gate structure was capable of injecting hot minority carriers into a gate dielectric. Fields required were about 3 times lower than required for p-n junction avalanche and 4 times lower than required for straight surface avalanche of MOS capacitors. The stacked gate electrode device is not found in conventional circuits and any instability caused by injection of carriers under such conditions is not a problem in practical devices.
In 1973, Verway reported in the Journal of Applied Physics, Vol. 44, No. 6, June 1973, pages 2681-2687, that hot minority carriers could be injected under non-avalanche conditions provided that a sufficiently high reverse bias (less than the avalanche breakdown voltage) was applied to the source and drain in the presence of (1) a sufficiently high gate voltage and (2) a continiously forward biased p-n junction located below the channel region. The forward biased p-n junction was used to provide carriers in the presence of a fixed field across the dielectric which created a steady state depletion region. Various non-volatile memory device structures based on the non-avalanche injection phenomenon are found in U.S. Pat. No. 3,893,151 to Bosselaar et al., including the use of light to provide a sufficient number of minority carriers. The use of drain avalanche in an MOSFET to provide charge cancelling injection of majority carriers is also described. Ning and Yu studied the trapping efficiency of the dielectric, the capture cross sections, and concentrations of electron traps in silicon dioxide layers by using optically induced hot-electron injection, Journal of Applied Physics, Vol. 45, No. 12, December 1975, pages 5373-5378. Since production quantities of MOSFET devices are not fabricated with an underlying p-n junction and are not utilized in an optically active environment, such abnormal conditions prove to be of little economic value in a manufacturing environment.
Abbas and Dockerty reported in Applied Physics Letters, Vol. 27, No. 3., Aug. 1, 1975, pages 147-148, that sub-avalanche injection of minority carriers may take place in small MOSFET devices operated in the normal range of operation. They also indicated that nitride passivated MOSFETs were particularly susceptible to threshold drift because of the large quantity of traps present at the nitride/oxide interface of the dual dielectric structure. They reported at the 1975 International Electron Devices Meeting, Dec. 1-3, 1975 that the earlier reported phenomenon was particularly sensitive to applied gate-to-drain voltage and channel length and that carriers were found to be injected only at the drain end of the channel, as in the drain avalanche condition, see Technical Digest 1975 IEDM, paper 3.2, pages 35-38 (1975). Instabilities in conventional MOSFETs due to the hot electron injection observed by Abbas and Dockerty may be controlled by increasing substrate resistivity and insuring that maximum source-to-drain and gate-to-drain voltage conditions are not exceeded during device operation.
Ning, Osburn and Yu reported in Applied Physics Letters, Vol. 29, No. 3, Aug. 1, 1976, pages 198-200, that yet another instability mechanism was found to cause variations in MOSFET device thresholds even when the conditions observed by Abbas and Dockerty were not exceeded. Ning et al found that minority carriers could be injected into the dielectric of n-channel MOSFETs by applying a negative bias to the substrate and a positive bias to the gate, with the source and drain junctions grounded. Thermally generated leakage current was found to provide sufficient free minority carriers which in the presence of a gate induced depletion layer of a MOSFET provides favorable conditions for non-avalanche injection of carriers into the gate dielectric. Although normal leakage induced alteration of device parameters is an extremely slow process, changes may occur over a period of thousands of hours which can effect device reliability over the expected life time of the device, particularly at elevated temperatures. Ning et al. reported FET threshold shifts on the order of a few hundred millivolts over a few hours under conditions intended to enhance the minority carrier injection. These conditions included low resitivity semiconductor substrate and elevated temperatures, i.e. higher leakage rate. Conventional silicon nitride passivated FETs have been shown to potentially exhibit threshold voltage changes of over 3 volts when operated over many tens of thousands of hours. In order to evaluate the reliability effects of leakage induced threshold shift as a function of device processing parameters and device design characteristics, extended static stress tests similar to those of Ning et al have been used which take many thousands of hours to obtain useful results.
In summary, various distinctly different instability phenomena have been observed which alter the operating characteristics of MOS devices. Most of these have either been found not to occur in normal operating environments or are known to be avoidable by proper device design or by the use of controlled operating conditions. Thermally generated leakage current has recently been found to be the source of an inherent carrier injection phenomenon which, although the effect is to some extent reducible, is not avoidable. Device reliability effects of leakage induced threshold shift are presently determinable only over an extremely extended period of time. While minority carrier generating mechanisms such as light and/or burried p-n junctions have been used to artificially create sufficient free carriers to observe threshold shifts, these techniques have the disadvantage of not being compatable with current manufacturing techniques used in MOSFET production.
Additional prior art which may be considered to be pertinent to the injection of minority carriers in semiconductor devices include U.S. Pat. No. 3,569,799 of Fang et al., assigned to the assignee of the instant invention, which relates to the forward and reverse biasing of a p-n junction in the vicinity of a negative resistance exhibiting dielectric in which avalanche breakdown conditions are used to alter the conductivity of the dielectric and U.S. Pat. No. 3,858,232 of Boyle et al. which teaches the use of a forward biased p-n junction as a source of minority carriers in a charge coupled shift register.